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Integrated Circuit Systems, Inc.
ICS85454-01
DUAL 2:1/1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
FEATURES
* Dual 2:1/1:2 MUX * Three LVDS outputs * Three differential inputs * Differential inputs can accept the following differential levels: LVPECL, LVDS, CML * Loopback test mode available * Maximum output frequency: 2.5GHz * Part-to-part skew: 250ps (maximum) * Additive phase jitter, RMS: 0.05ps (typical) * Propagation delay: 550ps (maximum) * 2.5V operating supply * -40C to 85C ambient operating temperature * Available in both standard and lead-free RoHS compliant packages
GENERAL DESCRIPTION
The ICS85454-01 is a 2:1/1:2 Multiplexer and a member of the HiPerClockSTM family of high HiPerClockSTM performance clock solutions from ICS. The 2:1 Multiplexer allows one of 2 inputs to be selected onto one output pin and the 1:2 MUX switches one input to both of two outputs. This device may be useful for multiplexing multi-rate Ethernet PHYs which have 100Mbit and 1000Mbit transmit/receive pairs onto an optical SFP module which has a single transmit/receive pair. Another mode allows loop back testing and allows the output of a PHY transmit pair to be routed to the PHY input pair. For examples, please refer to the Application Information section of the data sheet.
IC S
The ICS85454-01 is optimized for applications requiring very high performance and has a maximum operating frequency in 2.5GHz. The device is packaged in a small, 3mm x 3mm VFQFN package, making it ideal for use on space-constrained boards.
BLOCK DIAGRAM
SELB
PIN ASSIGNMENT
SELA nQB VDD QB
INA0 nINA0 QA0 1 nQA0 2 INB nINB
16 15 14 13 12 11 10 9 5
INB
INA0 nINA0 INA1 nINA1
LOOP0
0
QA0 nQA0
QA1 3 nQA1 4 6
nINB
7
SELB
8
GND
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0
QB nQB
1
1
INA1 nINA1
ICS85454-01
16-Lead VFQFN 3mm x 3mm x 0.95 package body K Package Top View
LOOP1
QA1 nQA1
SELA
85454AK-01
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Integrated Circuit Systems, Inc.
ICS85454-01
DUAL 2:1/1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Type Description Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Pulldown Non-inver ting differential clock input. Pullup/ Inver ting differential clock input. VDD/2 default when left floating. Pulldown Select pin for QAx outputs. When HIGH, selects same inputs used for Pulldown QB output. When LOW, selects INB input. LVCMOS/LVTTL interface levels. Power supply ground. Pullup/ Inver ting differential clock input. VDD/2 default when left floating. Pulldown Pulldown Non-inver ting differential clock input. Pullup/ Inver ting differential clock input. VDD/2 default when left floating. Pulldown Pulldown Non-inver ting differential clock input.
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 4 5 6 7 8 9 10 11 12 13 Name QA0, nQA0 QA1, nQA1 INB nINB SEL B GND nINA1 INA1 nINA0 INA0 VDD Output Output Input Input Input Power Input Input Input Input Power
Positive supply pin. Select pin for QB outputs. When HIGH, selects INA1 input. 14 SELA Input Pulldown When LOW, selects INA0 input. LVCMOS/LVTTL interface levels. 15, 16 nQB, QB Output Differential output pair. LVDS interface levels. NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol RPULLDOWN RPULLUP Parameter Input Pulldown Resistor Input Pullup Resistor Test Conditions Minimum Typical 37.5 37.5 Maximum Units k k
TABLE 3. INPUT CONTROL FUNCTION TABLE
Control Inputs SELA 0 1 0 1 SELB 0 0 1 1 Mode LOOP0 selected LOOP1 selected Loopback mode: LOOP0 Loopback mode: LOOP1
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Integrated Circuit Systems, Inc.
ICS85454-01
DUAL 2:1/1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
4.6V -0.5V to VDD + 0.5V 10mA 15mA -65C to 150C 51.5C/W (0 lfpm) NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage t o the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, IO Continuous Current Surge Current Storage Temperature, TSTG Package Thermal Impedance, JA
(Junction-to-Ambient)
Operating Temperature Range, TA -40C to +85C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V 5%
Symbol VDD IDD Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 2.375 Typical 2.5 Maximum 2.625 90 Units V mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 2.5V 5%
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current SELA, SELB SELA, SELB VDD = VIN = 2.625V VDD = 2.625V, VIN = 0V -150 Test Conditions Minimum 1.7 0 Typical Maximum VDD + 0.3 0.7 150 Units V V A A
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 2.5V 5%
Symbol IIH Parameter Input High Current Min -40C Typ Max Min 25C Typ Max Min 85C Typ Max Units A A V V
INAx, INB 150 150 150 nINAx, nINB INAx, INB IIL Input Low Current -150 -150 -150 nINAx, nINB VPP Peak-to-Peak Input Voltage 0.15 1.2 0.15 1.2 0.15 1.2 Commond Mode Input Voltage; VCMR 1.2 VDD 1.2 VDD 1.2 VDD NOTE 1, 2 NOTE 1: Common mode input voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for INAx, nINAx and INB, nINB is VDD + 0.3V.
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Integrated Circuit Systems, Inc.
ICS85454-01
DUAL 2:1/1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
-40C Min 25 0 0.93 Typ 350 1.18 Max 450 30 1.43 10 0.97 1.22 Min 250 25C Typ 350 Max 450 30 1.47 10 1.02 1.27 Min 250 85C Typ 350 Max 450 30 1.52 10
TABLE 4D. LVDS DC CHARACTERISTICS, VDD = 2.5V 5%
Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change Units mV mV V mV
NOTE 1: Refer to Parameter Measurement Information, "2.5V Output Load Test Circuit" diagram.
TABLE 5. AC CHARACTERISTICS, VDD = 2.375V TO 2.625V
Symbol fMAX Parameter Output Frequency Propagation Delay; NOTE 1 Par t-to-Par t Skew; NOTE 2, 3 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section MUX Isolation Output Rise/Fall Time INAx to QB or INB to QAx INAx to QAx = 622.08MHz, 12kHz - 20MHz @ 500MHz output 20% to 80% 50 250 300 250 0.05 55 250 Conditions Minimum Typical Maximum 2.5 550 650 Units GHz ps ps ps ps dB ps
tPD tsk(pp) tjit
M U X ISOLATION tR/tF
All parameters are measured 1.7GHz unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
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Integrated Circuit Systems, Inc.
ICS85454-01
DUAL 2:1/1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a
0 -10 -20 -30 -40 -50
ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter at 622.08MHz (12kHz - 20MHz) = 0.05ps (typical)
SSB PHASE NOISE dBc/HZ
-60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 10 100 1k 10k 100k 1M 10M 100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated
above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment.
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Integrated Circuit Systems, Inc.
ICS85454-01
DUAL 2:1/1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
PARAMETER MEASUREMENT INFORMATION
VDD
Qx
2.5V5% POWER SUPPLY
SCOPE
nINA0, nINA1 nINB
V
PP
+ Float GND -
LVDS
nQx
Cross Points
V
CMR
INA0, INA1 INB GND
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nINA0, nINA1 nINB INA0, INA1 INB nQA0, nQA1, nQB QA0, QA1, QB
nQx PART 1 Qx nQy PART 2 Qy
tsk(pp)
tPD
PART-TO-PART SKEW
PROPAGATION DELAY
VDD out
80% Clock Outputs
80% VSW I N G
DC Input
LVDS
100
VOD/ VOD out
20% tR tF
20%
OUTPUT RISE/FALL TIME
VDD out DC Input
DIFFERENTIAL OUTPUT VOLTAGE
out
VOS/ VOS
OFFSET VOLTAGE SETUP
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Integrated Circuit Systems, Inc.
ICS85454-01
DUAL 2:1/1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing.
VDD
R1 1K Single Ended Clock Input
IN
V_REF
nIN
C1 0.1u
R2 1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS:
IN/nIN INPUT: For applications not requiring the use of the differential input, both IN and nIN can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from IN to ground. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. LVDS All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, we recommend that there is no trace attached.
85454AK-01
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Integrated Circuit Systems, Inc.
ICS85454-01
DUAL 2:1/1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
DIFFERENTIAL CLOCK INPUT INTERFACE
The IN/nIN accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 2A to 2D show interface examples for the HiPerClockS IN/nIN input driven by the most common driver types. The input interfaces suggested here
3.3V 3.3V 3.3V R1 50 CML Zo = 50 Ohm IN Zo = 50 Ohm nIN HiPerClockS
Zo = 50 Ohm CML Built-In Pull-Up R1 100 nIN HiPerClockS IN 3.3V 3.3V Zo = 50 Ohm
R2 50
FIGURE 2A. HIPERCLOCKS IN/nIN INPUT DRIVEN BY AN OPEN COLLECTOR CML DRIVER
FIGURE 2B. HIPERCLOCKS IN/nIN INPUT DRIVEN BY A BUILT-IN PULLUP CML DRIVER
3.3V
3.3V Zo = 50 Ohm IN R1 100 Zo = 50 Ohm nIN HiPerClockS
3.3V 3.3V Zo = 50 Ohm
IN R1 100 Zo = 50 Ohm LVDS nIN HiPerClockS
LVDS
FIGURE 2C. HIPERCLOCKS IN/nIN INPUT DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 2D. HIPERCLOCKS IN/nIN INPUT DRIVEN BY A 3.3V LVDS DRIVER
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Integrated Circuit Systems, Inc.
ICS85454-01
DUAL 2:1/1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
TYPICAL APPLICATION DIAGRAM FOR HOST BUS ADAPTER BOARDS FOR ROUTING BETWEEN INTERNAL AND EXTERNAL CONNECTORS
Host Adapter Board
Internal Connector
SELB
INA0 nINA0
nINB
0 1
Protocol Controller
SerDes
QB nQB
QA0 nQA0
0 1
INA1 nINA1
QA1 nQA1
SELA
PCI Bus
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External Connector
INB
Integrated Circuit Systems, Inc.
ICS85454-01
DUAL 2:1/1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
TYPICAL APPLICATION DIAGRAM FOR HOT-SWAPPABLE LINKS TO REDUNDANT SWITCH FABRIC CARDS
SELB
LOOP 0
INA0 nINA0
TX SerDes
INB nINB
0 1
QA0 nQA0
QB nQB
0 1
INA1 nINA1 QA1 nQA1
Switch Fabric
RX
SELA
#0 LOOP 1 #1 Redundant Switch Card Backplane
Linecard
2.5V LVDS DRIVER TERMINATION
Figure 3 shows a typical termination for LVDS driver in characteristic impedance of 100 differential (50 single)
transmission line environment. For buffer with multiple LDVS driver, it is recommended to terminate the unused outputs.
2.5V 2.5V LVDS_Driv er + R1 100
-
100 Ohm Differential TransmissionLine 100 Differential Transmission Line
FIGURE 3. TYPICAL LVDS DRIVER TERMINATION
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Integrated Circuit Systems, Inc.
ICS85454-01
DUAL 2:1/1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85454-01. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS85454-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results.
*
Power_MAX = VDD_MAX * IDD_MAX = 2.625V * 90mA = 236.3mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow of and a multi-layer board, the appropriate value is 51.5C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.236W * 51.5C/W = 97.2C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA FOR 16-PIN VFQFN, FORCED CONVECTION
JA vs. 0 Air Flow (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards 51.5C/W
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Integrated Circuit Systems, Inc.
ICS85454-01
DUAL 2:1/1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE FOR 16 LEAD VFQFN
JA vs. 0 Air Flow (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards 51.5C/W
TRANSISTOR COUNT
The transistor count for ICS85454-01 is: 171
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Integrated Circuit Systems, Inc.
ICS85454-01
DUAL 2:1/1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
16 LEAD VFQFN
PACKAGE OUTLINE - K SUFFIX
FOR
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A3 b e ND NE D D2 E E2 L 1.0 0.30 1.0 3.0 1.8 0.50 0.18 0.50 BASIC 4 4 3.0 1.8 0.80 0 0.25 Reference 0.30 MINIMUM 16 1.0 0.05 MAXIMUM
Reference Document: JEDEC Publication 95, MO-220
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Integrated Circuit Systems, Inc.
ICS85454-01
DUAL 2:1/1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Package 16 Lead VFQFN 16 Lead VFQFN 16 Lead "Lead-Free" VFQFN 16 Lead "Lead-Free" VFQFN Shipping Packaging Tube 2500 Tape & Reel Tube 2500 Tape & Reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS85454AK-01 ICS85454AK-01T ICS85454AK-01LF ICS85454AK-01LFT Marking 5A01 5A01 A01L A01L
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 85454AK-01
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Integrated Circuit Systems, Inc.
ICS85454-01
DUAL 2:1/1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
REVISION HISTORY SHEET Description of Change LVDS DC Characteristics - changed VOD parameters. Changed VOD/VOS parameters from typical to maximum. Ordering Information - corrected Shipping Packaging from Tray to Tube. Package Dimension Table - corrected D2/E2 from 0.25min/1.25max. to 1.0min./1.8max. Date 3/14/06 6/16/06
Rev B
Table T4D T9
Page 4 14 13
B
T8
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